The present invention relates generally to semiconductor device fabrication and, more particularly, to device structures formed in the active layer of a silicon-on-insulator (SOI) substrate, methods of fabricating SOI device structures, and design structures for an integrated circuit including the SOI device structures.
To remain competitive with increased demands for computer processing power, semiconductor devices must constantly offer the ability to handle higher frequency signals with lower power consumption. To provide these performance increases, designers have been shrinking device dimensions, pushing the minimum feature size limitations of available semiconductor fabrication technologies. Silicon-on-insulator (SOI) technology has been developed to allow continued reductions in device size beyond what is possible with standard CMOS. Generally, a SOI wafer includes a top layer of thin SOI semiconductor material (e.g., silicon), a bulk substrate (e.g., a bulk silicon substrate or a silicon epilayer on a bulk silicon substrate), and a thin buried insulator layer, such as a buried oxide or BOX layer, physically separating and electrically isolating the SOI layer from the bulk substrate. The improved isolation and thinner active semiconductor regions provided by SOI allow devices to be formed with smaller dimensions, resulting in certain performance improvements over standard bulk semiconductor CMOS transistors, including higher speed switching and reduced power consumption at equivalent performance.
Semiconductor chips are regularly exposed to electrostatic discharge (ESD) events leading to potentially large and damaging currents within the integrated circuit. As semiconductor devices shrink, they become more susceptible to damage by ESD events. To prevent ESD damage, manufacturers of integrated circuits must take precautions to suppress ESD by including suppression devices on input and output pins. An effective ESD suppression device must be able to conduct large ESD currents safely away from sensitive devices without sustaining damage and, to avoid harming the performance of the protected circuit, must also avoid adding significantly to the capacitive loading of the input or output pin.
There is a need for improved device structures with designs that optimize device metrics such as failure current, junction capacitance, and on resistance, as well as methods of making these improved device structures and design structures for an integrated circuit including the improved device structure and fabricated using an SOI substrate.